1. Field of the Invention
The present invention relates generally to integrated circuits and to methods of forming anti-fuse structures used in fabricating integrated circuits. More particularly, the invention relates to methods of forming metal/amorphous silicon/metal anti-fuse structures which can be formed by the deposition of amorphous silicon on an unpatterned first metal layer.
2. State of the Art
Anti-fuse structures have been used in certain classes of integrated circuit (IC) chips, such as field programmable gate arrays, programmable read-only memories (PROMS) and the like. Field programmable gate arrays include a large number of logic elements, such as AND gates and OR gates, which can be selectively coupled together by means of anti-fuses to perform user designed functions. An unprogrammed anti-fuse type gate array is programmed by causing selected anti-fuses to become conductive.
Despite their being less popular than fuses, anti-fuses have the very desirable feature of being smaller in size than fuses. For example, a TiW fuse with a 2 .mu.m neck and 6 .mu.m end widths permits approximately 4,000 fuses to be provided on a typical device. In contrast, a 1 or 1.2 .mu.m diameter anti-fuse via permits 80,000 to 100,000 fuses to be provided on a single device. Therefore, anti-fuse-based technology can provide significantly greater numbers of interconnections per device and greater storage capacity than can devices based on fuse technology.
Anti-fuses include a material which initially has a high resistance, but which can be converted into a low resistance material by the application of a programming voltage. For example, amorphous silicon, which has an intrinsic resistivity of approximately 1 mega-ohm/cm, can be fashioned into 1 .mu.m wide link vias having a resistance of approximately 1 to 2 giga-ohms/cm.
These link vias can then be melted and recrystallized by the application of a programming voltage in the range of 10 to 12 volts d.c. to form link vias having a resistance less than 200 ohms. These low resistance vias can, for example, couple together logic elements of a field programmable gate array so that the gate array will perform user-desired functions, or can serve as memory cells of a PROM.
Among the prior art methods for forming anti-fuse structures, U.S. Pat. No. 5,328,865 discloses a method in which cusp-free anti-fuse structures are produced. In accordance with that method, an anti-fuse layer is formed directly on a conductive base layer, and anti-fuse islands are patterned on the unpatterned conductive base layer. Such process can be particularly problematic in the anti-fuse island patterning step, since the etching process is highly dependent upon selectivity of the anti-fuse material versus the underlying conductive base layer. Thus, overetching into the underlying conductive base layer may result.